if ( (mmio_bar == 0) || ( (mmio_bar & 0x3FFF) != 0 ) ) {
dprintk(XENLOG_ERR ,
- "AMD IOMMU: Invalid MMIO_BAR = 0x%lx\n", mmio_bar);
+ "AMD IOMMU: Invalid MMIO_BAR = 0x%"PRIx64"\n", mmio_bar);
return -ENODEV;
}
return NULL;
}
-void amd_iommu_setup_domain_device(struct domain *domain,
- struct amd_iommu *iommu, int requestor_id)
+void amd_iommu_setup_domain_device(
+ struct domain *domain, struct amd_iommu *iommu, int requestor_id)
{
void *dte;
u64 root_ptr;
root_ptr, hd->domain_id, hd->paging_mode);
dprintk(XENLOG_INFO, "AMD IOMMU: Set DTE req_id:%x, "
- "root_ptr:%lx, domain_id:%d, paging_mode:%d\n",
- requestor_id, root_ptr, hd->domain_id, hd->paging_mode);
+ "root_ptr:%"PRIx64", domain_id:%d, paging_mode:%d\n",
+ requestor_id, root_ptr, hd->domain_id, hd->paging_mode);
spin_unlock_irqrestore(&iommu->lock, flags);
}